If you balloon the clearance requirements to 0.5mm, it will prevent you from placing vias too close, but your trace clearance is (and probably needs to be) much tighter than 0.5mm.Īn improved clearance setting would have one value for traces, another for holes (even on the same net!), another for board edges, and probably another (IMO) for mask edges. If I hit 'g' to drag the via, it will highlight the clearance violation: You can see how the gray outline, representing the 0.2mm trace clearance in this example with all the defaults, is merely bubbled around the via outline. For better or worse, Kicad only respects the Board Setup -> Design Rules -> Net Classes -> Clearance setting when placing vias (AFAIK).
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